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Document Number: 70189
S-40807-Rev. J, 26-Apr-04
Vishay Siliconix
Si786
Product is End of Life 3/2014
Both minimum capacitance and maximum ESR require-
ments must be met. In order to get the low ESR, a capaci-
tance value of two to three times greater than the required
minimum may be necessary.
The equation for output ripple in continuous current mode is:
The equations for capacitive and resistive components of the
ripple in pulse-skipping mode are:
The total ripple, V
OUT(RPL)
, can be approximated as follows:
if
V
OUT(RPL)
(R) < 0.5 V
OUT(RPL)
(C),
then
V
OUT(RPL)
= V
OUT(RPL)
(C),
otherwise, V
OUT(RPL)
= 0.5 V
OUT(RPL)
(C) +
V
OUT(RPL)
(R).
Lower Voltage Input
The application circuit shown here can be easily modified to
work with 5.5 V to 12 V input voltages. Oscillation frequency
should be set at 200 kHz and increase the output capaci-
tance to 660 礔 on the 5 V output to maintain stable perfor-
mance up to 2 A of load current. Operation on the 3.3 V
supply will not be affected by this reduced input voltage.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?70189.
OUT(RPL)
I
LPP(MAX)
ESR
CF
1
2
xf C
F
+
x
x
x
+
x
OUT(RPL)
(C)
(4)
10
- 4
(L)
R
2
C
F
1
V
OUT
1
V
IN
- V
OUT
OUT(RPL)
(R)
(0.02)
ESR
CF
R
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